| US 7,612,597 B2 | ||
| Electronic circuit | ||
| Shuuji Matsumoto, Sagamihara (Japan) | ||
| Assigned to Kabushiki Kaisha Toshiba, Tokyo (Japan) | ||
| Filed on Aug. 30, 2007, as Appl. No. 11/847,871. | ||
| Claims priority of application No. 2006-238744 (JP), filed on Sep. 04, 2006. | ||
| Prior Publication US 2008/0054977 A1, Mar. 06, 2008 | ||
| Int. Cl. G06F 1/04 (2006.01); H03K 3/00 (2006.01) | ||
| U.S. Cl. 327—291 [327/293; 327/294; 327/298; 327/299] | 4 Claims |
| 1. An electronic circuit for performing clock gating on a clock signal supplied to a clock system using both edges, comprising:
a non-inverted/inverted signal selector which has an input connected to an input terminal, is fed with the clock signal through
the input terminal, and outputs a first signal obtained by non-inverting or inverting the clock signal in response to a control
signal;
a signal latch which has an input connected to an output of the non-inverted/inverted signal selector, outputs the inputted
first signal as a second signal through an output terminal, and latches a state of the second signal in response to an enable
signal inputted through an enable terminal; and
an input/output comparator which compares the clock signal and the second signal and outputs the control signal to the non-inverted/inverted
signal selector such that the first signal agrees with the second signal,
wherein the non-inverted/inverted signal selector includes an inverter which has an input connected to the input terminal,
and a multiplexer which has a first input connected to the input terminal and a second input connected to an output of the
inverter, switches signals inputted to the first input and the second input in response to the control signal inputted to
a selecting/input terminal, and outputs the first signal,
the signal latch includes a latch circuit which has a D input connected to an output of the multiplexer and a G input connected
to the enable terminal, outputs the inputted first signal as the second signal through the output terminal, and latches the
state of the second signal in response to the enable signal inputted through the enable terminal, and
the input/output comparator includes an exclusive-OR circuit which has one input connected to the input terminal, the other
input connected to the output terminal, and an output connected to the selecting/input terminal of the multiplexer, and compares
the clock signal and the second signal to output the control signal such that the first signal agrees with the second signal.
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