| US 7,612,580 B2 | ||
| Reduced power output buffer | ||
| Jie Chen, Saratoga, Calif. (US); Ting-Yen Chiang, Palo Alto, Calif. (US); Kuang-Yu Chen, Saratoga, Calif. (US); Chen Yu Wang, San Jose, Calif. (US); and Joe Froniewski, Palo Alto, Calif. (US) | ||
| Assigned to Silego Technology, Inc., Santa Clara, Calif. (US) | ||
| Filed on Feb. 15, 2008, as Appl. No. 12/70,374. | ||
| Application 12/070374 is a continuation of application No. 11/069921, filed on Feb. 28, 2005, granted, now 7,358,772. | ||
| Prior Publication US 2008/0204070 A1, Aug. 28, 2008 | ||
| This patent is subject to a terminal disclaimer. | ||
| Int. Cl. H03K 19/0175 (2006.01) | ||
| U.S. Cl. 326—30 [326/27] | 29 Claims |
| 1. A clock driving circuit for a PC architecture including:
a clock generating circuit coupled to an output buffer for the PC having a plurality of output lines connected to a plurality
of output loads having output load impedances, wherein the output lines are driven differentially at an output voltage lower
than a supply voltage;
a voltage node having a voltage node impedance, wherein the voltage node is maintained at substantially the output voltage;
and
a current sinking transistor that sinks current from the voltage node, wherein the current sinking transistor is operated
in a linear region characterized by an ohmic resistance determined by the size of the current sinking transistor;
a current sourcing transistor that supplies current to the voltage node, wherein the drain of the current sourcing transistor
is maintained at a reference voltage that is lower than the supply voltage;
wherein the impedance of the voltage node is matched to one of the load impedances by sizing the current sinking transistor.
|