| US 7,612,578 B2 | ||
| Semiconductor device, test system and method of testing on die termination circuit | ||
| Young-Uk Chang, Suwon-si (Korea, Republic of); Dong-Ho Hyun, Suwon-si (Korea, Republic of); and Seok-Won Hwang, Seoul (Korea, Republic of) | ||
| Assigned to Samsung Electronics Co., Ltd., (Korea, Republic of) | ||
| Filed on Oct. 24, 2006, as Appl. No. 11/585,615. | ||
| Claims priority of application No. 10-2005-0104827 (KR), filed on Nov. 03, 2005. | ||
| Prior Publication US 2007/0103189 A1, May 10, 2007 | ||
| Int. Cl. H03K 17/16 (2006.01); H03K 19/003 (2006.01); G06F 13/00 (2006.01) | ||
| U.S. Cl. 326—30 [326/21; 710/32] | 18 Claims |
| 1. A semiconductor device comprising:
a termination impedance control circuit configured to generate a termination impedance control signal in response to a test
mode command;
an on die termination (ODT) circuit coupled to a plurality of pads and configured to generate a plurality of termination impedances;
and
a boundary scan circuit configured to store the termination impedances to sequentially output the stored termination impedances,
wherein the termination impedances are sequentially outputted through one pin,
wherein the boundary scan circuit includes boundary scan registers cascade-connected with each other, and
wherein the boundary scan registers respectively store the termination impedances to sequentially output the termination impedances
by a shifting operation.
|