| US 7,612,416 B2 | ||
| Semiconductor device having a conductive portion below an interlayer insulating film and method for producing the same | ||
| Kiyoshi Takeuchi, Tokyo (Japan); Koichi Terashima, Tokyo (Japan); Hitoshi Wakabayashi, Tokyo (Japan); Shigeharu Yamagami, Tokyo (Japan); Atsushi Ogura, Tokyo (Japan); Masayasu Tanaka, Tokyo (Japan); Masahiro Nomura, Tokyo (Japan); Koichi Takeda, Tokyo (Japan); Toru Tatsumi, Tokyo (Japan); and Koji Watanabe, Tokyo (Japan) | ||
| Assigned to NEC Corporation, Tokyo (Japan) | ||
| Appl. No. 10/575,631 PCT Filed Sep. 29, 2004, PCT No. PCT/JP2004/014243 § 371(c)(1), (2), (4) Date Jan. 30, 2007, PCT Pub. No. WO2005/036651, PCT Pub. Date Apr. 21, 2005. |
||
| Claims priority of application No. 2003-351029 (JP), filed on Oct. 09, 2003; and application No. 2004-271506 (JP), filed on Sep. 17, 2004. | ||
| Prior Publication US 2007/0132009 A1, Jun. 14, 2007 | ||
| Int. Cl. H01L 27/01 (2006.01) | ||
| U.S. Cl. 257—377 [257/347; 257/E29.299] | 14 Claims |
| 1. A semiconductor device comprising:
a MIS type field effect transistor which comprises a semiconductor raised portion protruding from a substrate plane, a gate
electrode extending over the semiconductor raised portion from the top onto the opposite side faces of the semiconductor raised
portion, a gate insulation film existing between the gate electrode and the semiconductor raised portion, and source and drain
regions provided in the semiconductor raised portion;
an interlayer insulating film provided on a substrate including the transistor; and
a buried conductor interconnect that is formed by filling in a trench formed in the interlayer insulating film with a conductor,
wherein the buried conductor interconnect connects one of the source and drain regions of the semiconductor raised portion
and another conductive portion below the interlayer insulating film.
|