| US 7,612,413 B2 | ||
| Semiconductor device and manufacturing method thereof | ||
| Masato Koyama, Miura-gun (Japan); Reika Ichihara, Yokohama (Japan); Yoshinori Tsuchiya, Yokohama (Japan); Yuuichi Kamimuta, Yokohama (Japan); and Akira Nishiyama, Yokohama (Japan) | ||
| Assigned to Kabushiki Kaisha Toshiba, Tokyo (Japan) | ||
| Filed on Aug. 01, 2006, as Appl. No. 11/461,646. | ||
| Claims priority of application No. 2005-338789 (JP), filed on Nov. 24, 2005. | ||
| Prior Publication US 2007/0145488 A1, Jun. 28, 2007 | ||
| Int. Cl. H01L 27/092 (2006.01) | ||
| U.S. Cl. 257—369 [257/E21.635] | 15 Claims |
| 1. A semiconductor device comprising:
a substrate;
an n-type semiconductor region formed on the substrate;
a p-type semiconductor region formed on the substrate so as to be insulated and separated from the n type semiconductor region;
a p-channel metal insulator semiconductor (MIS) transistor formed on the n-type semiconductor region, the p-channel MIS transistor
comprising:
a first gate dielectric film formed on the n-type semiconductor region;
a first lower gate electrode made of an alloy of Ta and C and formed on the first gate dielectric film; and
a first upper gate electrode including silicon and formed on the first lower gate electrode; and
an n-channel MIS transistor formed on the p type semiconductor region, the n-channel MIS transistor comprising:
a second gate dielectric film formed on the p type semiconductor region;
a second lower gate electrode made of an alloy of Ta and C and formed on the second gate dielectric film; and
a second upper gate electrode including silicon and formed on the second lower gate electrode, and
a mole ratio of C to Ta (C/Ta) in the first lower gate electrode and the second lower gate electrode being from 2 to 4, and
the alloy of Ta and C in each of the first lower gate electrode and the second lower gate electrodes being amorphous.
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