a dielectric layer having a planar surface;

a memory device and an access device located above the planar surface of the dielectric layer, wherein

the memory device has a channel region provided on a first surface of a semiconductor layer, a gate structure above the channel region, and a threshold voltage; and

the access device has a channel region provided on a second surface of the semiconductor layer, and a gate structure above the channel region, the second surface being provided on an opposite side of the semiconductor layer relative to the first surface, wherein the semiconductor layer is thick enough to substantially isolate the gate structure of the access device from the gate structure of the memory device, such that the threshold voltage of the memory device is substantially unchanged over a predetermined range of voltages applied on the gate structure of the access device that renders the access device conducting.