| US 7,612,401 B2 | ||
| Non-volatile memory cell | ||
| Yoshio Ozawa, Yokohama (Japan); Shigehiko Saida, Yokkaichi (Japan); Yuji Takeuchi, Yokohama (Japan); and Masanobu Saito, Chiba (Japan) | ||
| Assigned to Kabushiki Kaisha Toshiba, Tokyo (Japan) | ||
| Filed on Jan. 25, 2006, as Appl. No. 11/338,654. | ||
| Application 11/338654 is a division of application No. 10/812987, filed on Mar. 31, 2004, granted, now 7,081,386. | ||
| Claims priority of application No. 2003-149335 (JP), filed on May 27, 2003. | ||
| Prior Publication US 2006/0131641 A1, Jun. 22, 2006 | ||
| Int. Cl. H01L 27/108 (2006.01); H01L 29/94 (2006.01) | ||
| U.S. Cl. 257—314 [257/E21.625; 257/E21.639; 257/E21.662; 257/315; 257/316; 438/257; 438/263; 438/264; 438/201; 438/211] | 4 Claims |
| 1. A semiconductor device comprising:
a semiconductor substrate having at least two isolation trenches that are approximately parallel to each other; and
a non-volatile memory cell provided on the semiconductor substrate,
the non-volatile memory cell comprising:
a tunnel insulating film having a film thickness changing continuously and with three or more periodic, undulating intervals
between successive and similar changes in a channel width direction of the non-volatile memory cell, wherein the channel width
direction is approximately perpendicular to the isolation trenches;
a floating gate electrode provided on the tunnel insulating film;
a control gate electrode provided above the floating gate electrode; and
an interelectrode insulating film provided between the control gate electrode and the floating gate electrode.
|