| US 7,612,365 B2 | ||
| Strained silicon with elastic edge relaxation | ||
| Paul A. Clifton, Mountain View, Calif. (US) | ||
| Assigned to Acorn Technologies, Inc., Santa Monica, Calif. (US) | ||
| Filed on Feb. 25, 2008, as Appl. No. 12/36,969. | ||
| Application 12/036969 is a division of application No. 11/378730, filed on Mar. 17, 2006, granted, now 7,338,834. | ||
| Prior Publication US 2008/0213962 A1, Sep. 04, 2008 | ||
| Int. Cl. H01L 31/0336 (2006.01); H01L 21/00 (2006.01) | ||
| U.S. Cl. 257—19 [438/95] | 25 Claims |
| 1. A semiconductor device comprising at least one n-channel MOS field effect transistor and a substrate, the substrate comprising
silicon, each of the n-channel MOSFETs comprising:
a first layer comprising germanium formed over the substrate, the first layer having a thickness less than a first thickness
at which misfit dislocations form in the first layer, the first layer having a first lower interface in-plane lattice spacing
matched with a substrate interface lattice spacing characteristic of an interface region of the substrate;
a second layer comprising silicon formed over the first layer, the second layer having a second layer thickness, the second
layer having a second lower interface in-plane lattice spacing matched with a first layer upper interface in-plane lattice
spacing characteristic of an upper interface of the first layer; and
a gate dielectric layer on the second layer and separating the second layer from a gate electrode, wherein a concentration
of germanium in the first layer is greater than a concentration of germanium in the second layer, the first layer and the
second layer having a lateral extent along one direction such that the second layer exhibits in-plane tensile strain over
all of the lateral extent through edge relaxation.
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