| US 7,612,359 B2 | ||
| Microelectronic devices using sacrificial layers and structures fabricated by same | ||
| Suk-Hun Choi, Gyeonggi-do (Korea, Republic of); Yoon-Ho Son, Gyeonggi-do (Korea, Republic of); Sung-Lae Cho, Gyeonggi-do (Korea, Republic of); and Joon-Sang Park, Gyeonggi-do (Korea, Republic of) | ||
| Assigned to Samsung Electronics Co., Ltd., (Korea, Republic of) | ||
| Filed on Sep. 25, 2007, as Appl. No. 11/860,674. | ||
| Application 11/860674 is a division of application No. 10/873388, filed on Jun. 22, 2004, granted, now 7,291,556. | ||
| Claims priority of application No. 2003-90874 (KR), filed on Dec. 12, 2003; and application No. 2004-22720 (KR), filed on Apr. 01, 2004. | ||
| Prior Publication US 2008/0011999 A1, Jan. 17, 2008 | ||
| Int. Cl. H01L 29/02 (2006.01) | ||
| U.S. Cl. 257—2 [257/3; 257/4; 257/E31.029; 365/148] | 12 Claims |
| 1. A phase-change memory device, comprising:
a microelectronic substrate including a first conductive region;
a silicon nitride layer and/or a silicon oxynitride layer on the first conductive region;
a contact plug extending from a surface of the silicon nitride layer and/or a silicon oxynitride layer through an opening
therein to the first conductive region;
a phase changeable material region on the contact plug and the silicon nitride layer and/or a silicon oxynitride layer; and
a second conductive region on the phase changeable material region.
|