| US 7,611,980 B2 | ||
| Single spacer process for multiplying pitch by a factor greater than two and related intermediate IC structures | ||
| David H. Wells, Boise, Id. (US); and Mirzafer K. Abatchev, Boise, Id. (US) | ||
| Assigned to Micron Technology, Inc., Boise, Id. (US) | ||
| Filed on Aug. 30, 2006, as Appl. No. 11/514,117. | ||
| Prior Publication US 2008/0057692 A1, Mar. 06, 2008 | ||
| Int. Cl. H01L 21/44 (2006.01); H01L 21/311 (2006.01) | ||
| U.S. Cl. 438—597 [438/424; 438/702; 438/942; 438/947; 257/435; 257/797; 257/798; 257/E21.023; 257/E21.035; 257/E21.038; 257/E21.24] | 18 Claims |
| 1. A method for fabricating an integrated circuit, comprising:
providing a first mandrel over a substrate, the first mandrel having a first width;
providing a second mandrel substantially over the first mandrel, the second mandrel having a second width smaller than the
first width;
providing a layer of spacer material on the first and second mandrels;
subjecting the layer of spacer material to a spacer etch, wherein the spacer etch simultaneously forms spacers on sidewalls
of the first and second mandrels;
selectively removing at least portions of the mandrels relative to the spacers to form a spacer pattern defined by the spacers;
and
processing the substrate through a mask defined by the spacer pattern.
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