| US 7,611,935 B2 | ||
| Gate straining in a semiconductor device | ||
| Zoran Krivokapic, Santa Clara, Calif. (US) | ||
| Assigned to Advanced Micro Devices, Inc., Austin, Tex. (US) | ||
| Filed on May 24, 2007, as Appl. No. 11/753,438. | ||
| Prior Publication US 2008/0293195 A1, Nov. 27, 2008 | ||
| Int. Cl. H01L 21/336 (2006.01); H01L 21/8234 (2006.01) | ||
| U.S. Cl. 438—197 [438/199; 257/E21.409; 257/E21.632] | 18 Claims |

| 1. A method of fabricating a semiconductor device, the method comprising:
providing a device structure on a semiconductor substrate, the device structure comprising a first spacer, a second spacer,
a gate opening formed between the first spacer and the second spacer, a first oxide region adjacent to and outside the first
spacer, and a second oxide region adjacent to and outside the second spacer;
filling the gate opening with a compressive insulating material;
forming a first conductive via in the first oxide region, and a second conductive via in the second oxide region;
thereafter removing the first oxide region and the second oxide region; and
depositing a tensile insulating material between the first conductive via and the first spacer, between the second conductive
via and the second spacer, and over the compressive insulating material;
wherein filling the gate opening with the compressive insulating material comprises:
depositing a first layer of compressive insulating material in the gate opening; and
depositing at least one additional layer of compressive insulating material on the first layer of compressive insulating material.
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