| US 7,610,542 B2 | ||
| Semiconductor memory in which error correction is performed by on-chip error correction circuit | ||
| Takeshi Nagai, Yokohama (Japan) | ||
| Assigned to Kabushiki Kaisha Toshiba, Tokyo (Japan) | ||
| Filed on Jun. 16, 2006, as Appl. No. 11/454,007. | ||
| Claims priority of application No. 2006-064428 (JP), filed on Mar. 09, 2006. | ||
| Prior Publication US 2007/0226590 A1, Sep. 27, 2007 | ||
| Int. Cl. G11C 29/00 (2006.01) | ||
| U.S. Cl. 714—763 [714/774] | 16 Claims |
| 1. A synchronous semiconductor memory which performs a pipeline operation, comprising:
an error correction circuit configured to correct an error of data read out from a memory cell;
a first write circuit configured to overwrite at least a portion of first write data externally input in response to a first
write command on the data read out from the memory cell and corrected by the error correction circuit, and write the overwritten
data in the memory cell;
an output circuit configured to output the overwritten data outside a chip; and
a second write circuit configured to reoverwrite at least a portion of externally input second write data on the overwritten
data between a cycle in which the first write command is input and a cycle in which the overwritten data is written in the
memory cell, encode the reoverwritten data, and write the encoded data in the memory cell.
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