| US 7,610,504 B2 | ||
| Semiconductor integrated circuit | ||
| Kohei Oikawa, Kamakura (Japan) | ||
| Assigned to Kabushiki Kaisha Toshiba, Tokyo (Japan) | ||
| Filed on Jul. 17, 2007, as Appl. No. 11/779,084. | ||
| Application 11/779084 is a division of application No. 10/934462, filed on Sep. 07, 2004, granted, now 7,272,743. | ||
| Claims priority of application No. 2004-217873 (JP), filed on Jul. 26, 2004. | ||
| Prior Publication US 2007/0296475 A1, Dec. 27, 2007 | ||
| Int. Cl. G06F 1/12 (2006.01); G06F 1/00 (2006.01) | ||
| U.S. Cl. 713—503 [713/400; 713/401; 713/500] | 13 Claims |
| 1. A semiconductor integrated circuit comprising:
a first power supply region supplied with a first power supply voltage, and having a first clock distribution network;
a second power supply region supplied with a second power supply voltage, and having a second clock distribution network;
a first phase synchronizer which provides a first output signal obtained by making a phase of a reference clock signal for
controlling a data input/output coincident with a phase of a clock signal at a first point of the first clock distribution
network, to a second point of the first clock distribution network; and
a second phase synchronizer which provides a second output signal obtained by making the phase of the reference clock signal
coincident with a phase of a clock signal at a first point of the second clock distribution network, to a second point of
the second clock distribution network,
wherein the semiconductor integrated circuit has a mode for changing a value of the second power supply voltage to a value
which is different from a value of the first power supply voltage.
|