| US 7,609,576 B2 | ||
| Semiconductor memory device with refresh trigger | ||
| Hiroshi Watanabe, Yokohama (Japan); and Tatsuya Tanaka, Yokohama (Japan) | ||
| Assigned to Kabushiki Kaisha Toshiba, Tokyo (Japan) | ||
| Filed on Aug. 27, 2007, as Appl. No. 11/845,337. | ||
| Claims priority of application No. 2007-020016 (JP), filed on Jan. 30, 2007. | ||
| Prior Publication US 2008/0181017 A1, Jul. 31, 2008 | ||
| Int. Cl. G11C 7/00 (2006.01) | ||
| U.S. Cl. 365—222 [365/185.25] | 20 Claims |
| 1. A semiconductor memory device comprising:
a memory cell array including a plurality of memory cell transistors;
an X decoder designating a position of an X axis of the memory cell;
a Y decoder designating a position of a Y axis crossing the X axis;
a controller collectively controlling operations of read, write and erase of the memory cell transistors via the X decoder
and the Y decoder;
a semiconductor time switch generating an output signal after a predetermined life time elapses without a power source; and
a refresh trigger circuit receiving the output signal from the semiconductor time switch, and giving the controller instructions
to transfer information stored in one area of the memory cell array to other area thereof to refresh the information.
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