a memory cell array having a plurality of electrically-programmable memory cells, said memory cells being multi-level cells, said memory cell array comprising,

a plurality of memory cell units, each memory cell unit including memory cells connected in series, each memory cell unit being connected to a source selection gate transistor at one end and to a drain selection gate transistor at the other end,

a plurality of word lines each connected to each of control gates of said memory cells, said plurality of word lines including a selected word line connected to a control gate of a selected memory cell to be programmed at a first time and then at a second time by applying to said selected word line a positive potential enough to turn on said selected memory cell before a next erasure operation, and a plurality of non-selected word lines except for said selected word line;

a plurality of bit lines each connected to said drain selection gate transistor of each of said plurality of said memory cell units; and

a source line commonly connected to the source side of said source selection gate transistor of each of said memory cell units,

wherein a potential applied to a non-selected word line adjacent to said selected word line at said second time of programming said selected memory cell is higher than a potential applied to said non-selected word line adjacent to said selected word line at said first time of programming said selected memory cell.