| US 7,609,551 B2 | ||
| Semiconductor memory device | ||
| Tomoaki Shino, Kawasaki (Japan); Akihiro Nitayama, Yokohama (Japan); Takeshi Hamamoto, Yokohama (Japan); Hideaki Aochi, Kawasaki (Japan); Takashi Ohsawa, Yokohama (Japan); and Ryo Fukuda, Yokohama (Japan) | ||
| Assigned to Kabushiki Kaisha Toshiba, Tokyo (Japan) | ||
| Filed on Sep. 25, 2007, as Appl. No. 11/860,956. | ||
| Claims priority of application No. 2006-268769 (JP), filed on Sep. 29, 2006. | ||
| Prior Publication US 2008/0237695 A1, Oct. 02, 2008 | ||
| Int. Cl. G11C 14/00 (2006.01); G11C 16/04 (2006.01) | ||
| U.S. Cl. 365—185.08 [365/149; 365/185.01] | 20 Claims |
| 15. A semiconductor memory device comprising:
a semiconductor layer;
a charge trapping film provided on a first surface of the semiconductor layer;
a gate insulating film provided on a second surface opposing the first surface of the semiconductor layer;
a back gate provided on the charge trapping film;
a front gate provided on the gate insulating film;
a source and a drain formed in the semiconductor layer; and
a body region which is provided between the drain and the source, the body region being in an electrically floating state,
wherein
the semiconductor memory device includes a first storage state for storing data depending on the number of majority carriers
in the body region and a second storage state for storing data depending on the amount of charges in the charge trapping film,
and
the data is stored in both states of the first storage state and the second storage state.
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