| US 7,609,543 B2 | ||
| Method and implementation of stress test for MRAM | ||
| Hsu Kai Yang, Pleasanton, Calif. (US); Lejan Pu, San Jose, Calif. (US); Perng-Fei Yuh, San Jose, Calif. (US); and Po-Kang Wang, San Jose, Calif. (US) | ||
| Assigned to MagIC Technologies, Inc., Milpitas, Calif. (US) | ||
| Filed on Sep. 27, 2007, as Appl. No. 11/904,434. | ||
| Prior Publication US 2009/0086531 A1, Apr. 02, 2009 | ||
| Int. Cl. G11C 11/00 (2006.01) | ||
| U.S. Cl. 365—158 [365/148; 365/201; 365/210.1] | 29 Claims |
| 1. A circuit for stressing memory cells, comprising:
a magnetic random access memory for storing data in resistance based memory cells, said resistance based memory cells accessed
by word lines and bit lines, wherein said bit lines comprise a cell block and are in communication with first and second data
buses;
wherein reference bit lines comprise a reference block and are in communication with said first and second data buses and
a reference bus,
wherein cell data, read from said cell block, are compared with an average resistance of a reference cell of said reference
block; and
a voltage stress circuit in communication with said magnetic random access memory, said voltage stress circuit applying a
controlled stress voltage to said resistance based memory cells, said stress voltage stressing said resistance based memory
cells by causing excess current to flow in those said resistance based memory cells subject to early failure.
|