| US 7,609,194 B2 | ||
| Clock signal generating device and analog-digital conversion device | ||
| Yoshikazu Makabe, Osaka (Japan); Ikuo Hidaka, Kyoto (Japan); Koji Oka, Osaka (Japan); and Toshiaki Ozeki, Osaka (Japan) | ||
| Assigned to Panasonic Corporation, Osaka (Japan) | ||
| Filed on Dec. 27, 2007, as Appl. No. 11/964,943. | ||
| Claims priority of application No. 2006-351203 (JP), filed on Dec. 27, 2006. | ||
| Prior Publication US 2008/0158035 A1, Jul. 03, 2008 | ||
| Int. Cl. H03M 1/12 (2006.01) | ||
| U.S. Cl. 341—155 [341/122] | 5 Claims |
| 1. A clock signal generating device comprising first, second and third Delayed Flip Flops, wherein
the first Delayed Flip Flop comprises:
a first D input terminal;
a first clock input terminal operable to receive a clock signal;
a first output terminal operable to hold and output a signal inputted to the first D input terminal, based on the clock signal;
and
a first inversion output terminal operable to invert and output the signal inputted to the first D input terminal and output
the signal to the first D input terminal as a feedback, based on the clock signal,
the second Delayed Flip Flop comprises:
a second D input terminal operable to receive the output from the first output terminal of the first Delayed Flip Flop;
a second clock input terminal operable to receive the clock signal; and
a second output terminal operable to hold a signal inputted to the second D input terminal and output the signal as a first
output, based on the clock signal,
the third Delayed Flip Flop comprises:
a third D input terminal operable to receive the output from the first inversion output terminal of the first Delayed Flip
Flop;
a third clock input terminal operable to receive the clock signal; and
a third output terminal operable to hold a signal inputted to the third D input terminal and output the signal as a second
output, based on the clock signal, and
wherein the first output from the second output terminal of the second Delayed Flip Flop and the second output from the third
output terminal of the third Delayed Flip Flop have signal waveforms inverted at the same timing,
wherein non-inversion outputs of the second Delayed Flip Flop and the third Delayed Flip Flop are same in timing with respect
to the clock signal.
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