a programmable delay line, the programmable delay line comprising a signal input, a signal output and a delay value input;

an inverter coupled between the signal input and the signal output; and

a delay select circuit, the delay select circuit comprises a first input having a first input data length, a second input having a second input data length and an output having a data length less than the combined data length of the first input and the second input;

wherein a signal received at the signal input is delayed by a time period based on a value received at the delay value input before appearing at the signal output

wherein the output of the delay select circuit is coupled to the delay value input of the programmable delay line; and

wherein the programmable delay line is responsive to delay the signal received at the signal input by an amount of time specified by the delay select circuit.