| US 7,609,070 B2 | ||
| Manufacturing method and controlling method of electronic device | ||
| Tomohiro Kagiyama, Yamanashi (Japan); Yasuhiro Tosaka, Yamanashi (Japan); and Norikazu Iwagami, Yamanashi (Japan) | ||
| Assigned to Eudyna Devices Inc., Yamanashi (Japan) | ||
| Filed on Sep. 21, 2007, as Appl. No. 11/902,392. | ||
| Claims priority of application No. 2006-258933 (JP), filed on Sep. 25, 2006. | ||
| Prior Publication US 2008/0074119 A1, Mar. 27, 2008 | ||
| Int. Cl. G01R 31/12 (2006.01); G01R 31/08 (2006.01); G01R 31/26 (2006.01) | ||
| U.S. Cl. 324—548 [324/522; 438/17] | 8 Claims |
| 1. A manufacturing method of an electronic device comprising:
applying a direct voltage having a first polarity to a capacitor that has an insulating layer including nitrogen and silicon
as a capacitor dielectric layer;
determining a nondefective capacitor and a defective capacitor by testing the capacitor to which the direct voltage having
the first polarity is applied; and
applying a direct voltage having a second polarity to the nondefective capacitor, the second polarity being opposite to the
first polarity, wherein the capacitor dielectric layer is composed of SiN or SiON.
|