| US 7,608,890 B2 | ||
| Semiconductor device and method of manufacturing semiconductor device | ||
| Atsushi Yagishita, Yokohama (Japan) | ||
| Assigned to Kabushiki Kaisha Toshiba, Tokyo (Japan) | ||
| Filed on Jun. 13, 2006, as Appl. No. 11/451,318. | ||
| Claims priority of application No. 2005-173606 (JP), filed on Jun. 14, 2005. | ||
| Prior Publication US 2007/0004117 A1, Jan. 04, 2007 | ||
| Int. Cl. H01L 27/108 (2006.01) | ||
| U.S. Cl. 257—347 [257/329; 257/E27.112] | 10 Claims |
| 1. A semiconductor device comprising:
an insulation layer;
a plurality of Fins arranged on the insulating film at a pitch smaller than a minimum pitch which includes a line and space
pattern;
gate insulation films formed on sidewalls of the Fins;
a gate electrode which extends in a direction of arrangement of the Fins and which is electrically insulated from the plurality
of Fins, the gate electrode being common in the plurality of Fins;
source-drain layers formed in portions of the Fins, the portions of the Fins being arranged on both sides of the gate electrode;
and
a metal or a metal silicide which is in contact with upper surfaces or side surfaces of the source-drain layers of the plurality
of Fins to connect the Fins to each other.
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