| US 7,608,886 B2 | ||
| Systems and methods for a high density, compact memory array | ||
| Tzu-Hsuan Hsu, Chiayi (Taiwan); Ming-Hsiu Lee, Hsinchu (Taiwan); Chao-I Wu, Tainan (Taiwan); and Ming-Chang Kuo, Changhua (Taiwan) | ||
| Assigned to Macronix International Co., Ltd., (Taiwan) | ||
| Filed on Jan. 06, 2006, as Appl. No. 11/327,792. | ||
| Prior Publication US 2007/0161193 A1, Jul. 12, 2007 | ||
| Int. Cl. H01L 29/792 (2006.01) | ||
| U.S. Cl. 257—324 [257/E21.679; 257/E29.309] | 31 Claims |
| 1. A memory array, comprising:
a first vertical memory cell comprising a first plurality of transistor structures;
a second vertical memory cell comprising a second plurality of transistor structures;
a joint drain region between the first and second memory cells;
a common source region between the first and the second memory cells; and
a joint body region between the first memory cell and the second memory cell,
wherein each of the first plurality of transistor structures share a first common conductive gate region wholly disposed above
the common source region.
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