| US 7,608,883 B2 | ||
| Transistor for non volatile memory devices having a carbon nanotube channel and electrically floating quantum dots in its gate dielectric | ||
| Marko Radosavljevic, Beaverton, Calif. (US); Amlan Majumdar, Portland, Oreg. (US); Suman Datta, Beaverton, Oreg. (US); Justin Brask, Portland, Oreg. (US); Brian Doyle, Beaverton, Calif. (US); and Robert Chau, Beaverton, Oreg. (US) | ||
| Assigned to Intel Corporation, Santa Clara, Calif. (US) | ||
| Filed on Feb. 28, 2008, as Appl. No. 12/72,971. | ||
| Application 12/072971 is a division of application No. 11/285763, filed on Nov. 21, 2005, granted, now 7,342,277. | ||
| Prior Publication US 2008/0151603 A1, Jun. 26, 2008 | ||
| Int. Cl. H01L 29/76 (2006.01) | ||
| U.S. Cl. 257—315 [257/317; 257/321; 257/324; 257/E29.3; 257/E29.304; 257/E29.316] | 6 Claims |
| 1. A method, comprising:
altering a threshold voltage of a transistor by creating a tunneling current that flows through dielectric material located
between a quantum dot and into a layer of conductive material, said quantum dot disposed in said dielectric material and located
between a carbon nanotube and said layer of conductive material, said transistor having said carbon nanotube electrically
coupled between source and drain electrodes, said layer of conductive material forming at least part of said transistor's
gate, wherein said electron tunneling current is substantially greater than second tunneling current, if any, between said
quantum dot and said carbon nanotube.
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