| US 7,608,882 B2 | ||
| Split-gate non-volatile memory | ||
| Hsiang-Lan Lung, Hsinchu (Taiwan); and Rui-Chen Liu, Hsinchu (Taiwan) | ||
| Assigned to MACRONIX International Co., Ltd., Hsinchu (Taiwan) | ||
| Filed on Aug. 11, 2003, as Appl. No. 10/604,692. | ||
| Prior Publication US 2005/0035393 A1, Feb. 17, 2005 | ||
| Int. Cl. H01L 29/788 (2006.01) | ||
| U.S. Cl. 257—315 [257/314; 257/320; 257/324; 257/E29.309] | 12 Claims |
| 1. A split-gate non-volatile memory cell, comprising:
a substrate;
a charge-trapping layer on the substrate;
a split gate as a whole located over the charge-trapping layer, being a part of one word line of a non-volatile memory array
including the split-gate non-volatile memory cell; and
a source/drain in the substrate beside the split gate,
wherein the split gate includes at least two neighboring conductive pieces that are shorted with each other and have two opposite
edge portions together causing, in operation of the memory cell, a locally stronger electric field such that only one coding
region is defined, by the two neighboring conductive pieces, in the charge-trapping layer around the two opposite edge portions.
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