| US 7,608,879 B2 | ||
| Semiconductor device including a capacitance | ||
| Shigenobu Maeda, Tokyo (Japan); Takashi Ipposhi, Tokyo (Japan); and Yuuichi Hirano, Tokyo (Japan) | ||
| Assigned to Renesas Technology Corp., Tokyo (Japan) | ||
| Filed on Aug. 17, 2007, as Appl. No. 11/840,612. | ||
| Application 11/840612 is a division of application No. 11/510582, filed on Aug. 28, 2006, granted, now 7,339,238. | ||
| Application 11/510582 is a division of application No. 10/995193, filed on Nov. 24, 2004, granted, now 7,112,835. | ||
| Application 10/995193 is a division of application No. 10/216722, filed on Aug. 13, 2002, granted, now 6,858,918. | ||
| Claims priority of application No. 2001-284866 (JP), filed on Sep. 19, 2001. | ||
| Prior Publication US 2007/0296009 A1, Dec. 27, 2007 | ||
| Int. Cl. H01L 29/94 (2006.01) | ||
| U.S. Cl. 257—296 [257/E29.345] | 2 Claims |
| 1. A semiconductor device comprising:
an insulated gate type capacitance formed in a semiconductor substrate,
said insulated gate type capacitance including,
a gate insulating film for said capacitance selectively formed on said semiconductor substrate,
a gate electrode for said capacitance formed on said gate insulating film for said capacitance and having opposed ends, and
extraction electrode regions formed to interpose therebetween a body region for said capacitance which is provided directly
below said gate electrode for said capacitance in a surface of said semiconductor substrate, and
said gate electrode for said capacitance having first and second contact pad portions of the opposed ends of the gate electrode,
wherein said first and second contact pad portions are electrically connected with a wiring.
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