| US 7,608,513 B2 | ||
| Dual gate LDMOS device fabrication methods | ||
| Hongning Yang, Chandler, Ariz. (US); Veronique C. Macary, Chandler, Ariz. (US); Won Gi Min, Chandler, Ariz. (US); and Jiang-Kai Zuo, Chandler, Ariz. (US) | ||
| Assigned to Freescale Semiconductor, Inc., Austin, Tex. (US) | ||
| Filed on Jan. 25, 2007, as Appl. No. 11/626,928. | ||
| Prior Publication US 2008/0182394 A1, Jul. 31, 2008 | ||
| Int. Cl. H01L 21/336 (2006.01) | ||
| U.S. Cl. 438—286 [257/E21.427] | 20 Claims |
| 1. A method of fabricating a semiconductor device, comprising the steps of:
providing a semiconductor having a substrate region of a first conductivity type and first impurity concentration, extending
to a surface of the semiconductor;
impurity doping a first region of the first conductivity type and a second dopant concentration in a first portion of the
substrate region to form a first doped well extending substantially to the surface;
impurity doping a second region of a second, opposite conductivity type and a third dopant concentration within a second portion
of the substrate region different from the first portion of the substrate region, thereby forming a second doped well extending
substantially to the surface;
forming a first gate dielectric surmounted by a first gate, at least partially overlying the first region or the substrate
region or both;
forming a second gate dielectric surmounted by a second gate, substantially overlying the second region and spaced apart from
the first gate;
impurity doping a third region of the second conductivity type and a fourth impurity concentration in the substrate region,
adapted when biased to form a depletion region at least partly in the substrate region or in a combination of the substrate
region and the first region;
forming a bias contact to a part of the depletion region; and
electrically coupling the bias contact to the second gate.
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