| US 7,608,504 B2 | ||
| Memory and manufacturing method thereof | ||
| Chien-Hung Liu, Taipei (Taiwan); Shou-Wei Huang, Hsinchu County (Taiwan); Ying-Tso Chen, Kaoshsiung County (Taiwan); and Yu-Tsung Lin, Taoyuan County (Taiwan) | ||
| Assigned to Macronix International Co., Ltd., Hsinchu (Taiwan) | ||
| Filed on Aug. 30, 2006, as Appl. No. 11/468,311. | ||
| Prior Publication US 2008/0054322 A1, Mar. 06, 2008 | ||
| Int. Cl. H01L 21/00 (2006.01) | ||
| U.S. Cl. 438—257 [438/276; 438/735] | 5 Claims |
| 1. A method of manufacturing a memory, comprising:
providing a substrate;
forming a first oxide-nitride-oxide (ONO) structure on the substrate, comprising:
forming a bottom oxide layer on the substrate;
forming a nitride layer on the bottom oxide layer; and
forming a top oxide layer on the nitride layer;
forming a plurality of bit lines in the substrate, and all of the bit lines disposed in parallel, and step of forming the
bit lines further comprising:
forming a patterned photo-resist layer on the first ONO structure, wherein the patterned photo-resist layer has a plurality
of openings for exposing part of the first ONO structure; and
forming the bit lines in the part of the substrate corresponding to the openings; and
forming a plurality of word lines on the substrate, wherein the word lines are crossed with but not perpendicular to the bit
lines.
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