	US 7,608,488 B2
	Semiconductor memory device and method of manufacturing the same
Yasuyuki Baba, Yokohama (Japan); and Susumu Yoshikawa, Yokohama (Japan)
Assigned to Kabushiki Kaisha Toshiba, Tokyo (Japan)
Filed on Oct. 18, 2007, as Appl. No. 11/874,481.
Claims priority of application No. 2006-292691 (JP), filed on Oct. 27, 2006.
Prior Publication US 2008/0258201 A1, Oct. 23, 2008
Int. Cl. H01L 21/82 (2006.01)

U.S. Cl. 438—128 [257/316; 257/E21.791; 438/294; 438/587]

7 Claims

1. A manufacturing method of a semiconductor memory device for manufacturing a first semiconductor device wherein a cell array ratio at which an area occupied by a memory cell array region with respect to the entire surface area of a semiconductor substrate is a predetermined ratio and a second semiconductor device wherein said cell array ratio is smaller than said predetermined ratio, said manufacturing method comprising:

forming a height of first element-isolating insulating films in a first memory cell array region of said first semiconductor device, wherein first electrode layers and the first element-isolating insulating films are initially formed with a first height from said semiconductor substrate, so as to be a second height smaller than the first height, by performing etching treatment under predetermined conditions using a reactive ion etching method upon the entirety of the first memory cell array region using a first etching mask having a first opening for exposing the entirety of said first memory cell array region and a ratio at which the area of said first opening occupies part of the entire surface area of said semiconductor substrate is a predetermined opening ratio; and

forming a height of second element-isolating insulating films in a second memory cell array region and part of peripheral circuit region of said second semiconductor device, wherein second electrode layers and the second element-isolating insulating films are initially formed with the first height from said semiconductor substrate, so as to be the same as said second height, by performing etching treatment under conditions same as said predetermined conditions using a reactive ion etching method upon the second memory cell array region and the part of peripheral circuit region using a second etching mask having a second opening for exposing the entirety of said second memory cell array region and a third opening for exposing part of said peripheral circuit region wherein a ratio at which the sum of the areas of said second and third openings occupies part of the entire surface area of said second semiconductor substrate is the same as said predetermined opening ratio.