| US 7,603,643 B2 | ||
| Method and system for conducting design explorations of an integrated circuit | ||
| Thaddeus Clay McCracken, Tigard, Oreg. (US); Jong-Chang Lee, Macungie, Pa. (US); Ping-Chih Wu, Cupertino, Calif. (US); Cecile Nghiem, Union City, Calif. (US); Kit Lam Cheong, Palo Alto, Calif. (US); and Patrick John Eichenseer, Austin, Tex. (US) | ||
| Assigned to Cadence Design Systems, Inc., San Jose, Calif. (US) | ||
| Filed on Jan. 30, 2007, as Appl. No. 11/700,284. | ||
| Prior Publication US 2008/0184184 A1, Jul. 31, 2008 | ||
| Int. Cl. G06F 17/50 (2006.01) | ||
| U.S. Cl. 716—10 [716/8; 716/9] | 24 Claims |
| 1. A computer implemented method for conducting design explorations of an integrated circuit, comprising:
obtaining a design description of the integrated circuit, wherein the design description includes a virtual design block;
creating a representative netlist for representing the virtual design block, wherein the representative netlist includes one
or more soft design models, and each soft design model comprises one or more template cells for modeling a portion of the
integrated circuit;
defining physical attributes for the one or more soft design models in accordance with one or more area requirements of the
virtual design block, wherein the one or more soft design models are described with flexible shape and flexible pin locations;
performing the design explorations of the integrated circuit using the one or more soft design models and their corresponding
template cells, wherein the act of performing the design exploration is performed by at least one processor, and the design
explorations are performed without requiring specifying a pin location;
generating a representative implementation of the integrated circuit using one or more results of the design explorations;
and
displaying the one or more results of the act of performing the one or more design explorations on a display apparatus or
storing the one or more results in a computer readable storage medium or a storage device.
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