| US 7,603,642 B2 | ||
| Placer with wires for RF and analog design | ||
| Pero Subasic, Santa Clara, Calif. (US); Xuejin Wang, Chandler, Ariz. (US); Enis A. Dengi, Tempe, Ariz. (US); and Ibraz H. Mohammed, Tempe, Ariz. (US) | ||
| Assigned to Cadence Design Systems, Inc., San Jose, Calif. (US) | ||
| Filed on Sep. 27, 2006, as Appl. No. 11/528,235. | ||
| Prior Publication US 2008/0077898 A1, Mar. 27, 2008 | ||
| Int. Cl. G06F 17/50 (2006.01) | ||
| U.S. Cl. 716—10 [716/12; 716/14] | 22 Claims |
| 1. A computer-implemented method of placement of components and networks (nets), utilized for interconnecting said components,
of a circuit layout, the method comprising:
(a) providing in a computer storage a solver operative under the control of a processor of the computer for implementing optimizing
software;
(b) inputting into the solver provided in the computer storage for each device of the circuit layout data regarding: (1) the
dimensions of said device, (2) each terminal of said device and (3) the connection of each terminal to at least one net of
the circuit layout;
(c) inputting into the solver provided in the computer storage for each pad (or land) of the circuit layout data regarding:
(1) the dimensions of said pad and (2) the connection of said pad to at least one net;
(d) inputting into the solver provided in the computer storage for each junction (or anchor) of a net of the circuit layout
data regarding the dimensions of said junction;
(e) inputting into the solver provided in the computer storage for each net or segment thereof data regarding: (1) at least
one dimension of said net or segment, (2) an orientation of said net or segment in the circuit layout, (3) the connection
of each terminal of said net or segment to a device, pad, or junction, and (4) the relative locations of the terminals of
said net or segment with respect to each other;
(f) inputting into the solver provided in the computer storage at least one intermediary that defines an imaginary line in
the circuit layout that is used as a reference for determining the position of at least one object of the circuit layout,
wherein each object is either a device, a pad, a junction, or a net or segment thereof;
(g) inputting into the solver provided in the computer storage at least one symmetry constraint that defines positional symmetry
between at least two objects of the circuit layout about an intermediary input in step (f);
(h) inputting into the solver provided in the computer storage at least one alignment constraint that defines an alignment
between at least two objects of the circuit;
(i) inputting into the solver provided in the computer storage a plurality of topological constraints, each of which defines
the relative position of at least two objects of the circuit layout;
(j) inputting into the solver provided in the computer storage at least one objective for the solver to attempt to satisfy
based on the constraints input to the solver, wherein the objective includes minimizing at least one of the area of the circuit
layout and a total length of the nets of the circuit layout; and
(k) causing the processor of the computer to execute the solver to process the input constraints subject to the input objective(s)
to simultaneously determine placements of the objects and the nets that is either (1) satisfactory, given a processing constraint
imposed on the solver that is not related per se to said placements, (2) legal and feasible, or (3) optimal.
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