| US 7,603,582 B2 | ||
| Systems and methods for CPU repair | ||
| Jeff Barlow, Roseville, Calif. (US); Jeff Brauch, Fort Collins, Colo. (US); Howard Calkin, Roseville, Calif. (US); Raymond Gratias, Fort Collins, Colo. (US); Stephen Hack, Fort Collins, Colo. (US); Lacey Joyal, Fort Collins, Colo. (US); Guy Kuntz, Richardson, Tex. (US); Ken Pomaranski, Roseville, Calif. (US); and Michael Sedmak, Fort Collins, Colo. (US) | ||
| Assigned to Hewlett-Packard Development Company, L.P., Houston, Tex. (US) | ||
| Filed on Feb. 17, 2006, as Appl. No. 11/356,576. | ||
| Claims priority of provisional application 60/654256, filed on Feb. 18, 2005. | ||
| Prior Publication US 2006/0230231 A1, Oct. 12, 2006 | ||
| Int. Cl. G06F 11/00 (2006.01) | ||
| U.S. Cl. 714—7 [714/42; 714/710] | 29 Claims |
| 1. A method of repairing a processor comprising the steps of:
assigning each cache element a quality rank based on each cache element's error rate;
comparing the quality rank of an allocated cache element to the quality rank of a non-allocated cache element; and
swapping in said non-allocated cache element for said allocated cache element based on said comparison.
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