| US 7,603,546 B2 | ||
| System, method and apparatus for dependency chain processing | ||
| Satish Narayanasamy, La Jolla, Calif. (US); Hong Wang, Santa Clara, Calif. (US); John Shen, San Jose, Calif. (US); Roni Rosner, Binyamina (Israel); Yoav Almog, Haifa (Israel); Naftali Schwartz, Yaakov (Israel); Gerolf Hoflehner, Santa Clara, Calif. (US); Daniel LaVery, Santa Clara, Calif. (US); Wei Li, Redwood, Calif. (US); Xinmin Tian, Union City, Calif. (US); Milind Girkar, Sunnyvale, Calif. (US); and Perry Wang, San Jose, Calif. (US) | ||
| Assigned to Intel Corporation, Santa Clara, Calif. (US) | ||
| Filed on Sep. 28, 2004, as Appl. No. 10/950,693. | ||
| Prior Publication US 2006/0070047 A1, Mar. 30, 2006 | ||
| Int. Cl. G06F 9/00 (2006.01); G06F 9/24 (2006.01); G06F 15/177 (2006.01) | ||
| U.S. Cl. 713—1 [717/144; 717/151; 717/159] | 22 Claims |
| 1. A method comprising:
splitting a dependency chain into a set of reduced-width dependency chains, wherein splitting said dependency chain comprises:
determining a plurality of splitting scenarios of said dependency chain, wherein the reduced-width dependency chains correspond
to a set of instructions and wherein the set of instructions are to be stored in a memory, wherein an instruction execution
trace is to be converted into a string of stream identifiers; and
compressing the string of stream identifiers to generate a directed acyclic graph, wherein one or more frequently recurrent
sequences of stream identifiers, corresponding to the set of reduced-width dependency chains, are to be determined based on
the directed acyclic graph.
|