tracking which instructions in a pipeline are ahead of a rejected instruction in the pipeline and therefore will be allowed to complete and which instructions in the pipeline follow in time the rejected instruction;

indicating whether the rejected instruction was a fast or slow reject; and

representing, for each individual cycle of an instruction currently passing through the pipeline, a lookahead state of the instruction as it passes through each stage of the pipeline; wherein the processor speculatively continues executing an instruction in a lookahead state during stalled periods, with the instruction that continues to execute during stalled periods being a lookahead instruction in that it does not fully execute to completion during the stalled periods, in order to generate addresses that will be needed when a stall period ends and normal dispatch resumes, wherein if the reject is a fast reject, calculating a dispatch cycle of the rejected instruction, starting a counter to count down to the dispatch cycle of the rejected instruction, executing instructions in the pipeline while the counter is counting down to the dispatch cycle of the rejected instruction, and after the counter has counted down to the dispatch cycle of the rejected instruction, resetting a lookahead state of a different given instruction in the pipeline for each one of a plurality of successive cycles to permit each one of a plurality of given instructions to complete.