| US 7,602,632 B2 | ||
| Multi-level memory cell utilizing measurement time delay as the characteristic parameter for level definition | ||
| Matthew J. Breitwisch, Westchester County, N.Y. (US); Chung H. Lam, Westchester County, N.Y. (US); and Bipin Rajendran, Westchester County, N.Y. (US) | ||
| Assigned to International Business Machines Corporation, Armonk, N.Y. (US) | ||
| Filed on Sep. 18, 2007, as Appl. No. 11/857,370. | ||
| Prior Publication US 2009/0073785 A1, Mar. 19, 2009 | ||
| This patent is subject to a terminal disclaimer. | ||
| Int. Cl. G11C 11/00 (2006.01) | ||
| U.S. Cl. 365—148 [365/203; 365/202] | 8 Claims |
| 1. A method for operating a memory cell in which a variation of the characteristic parameter of the memory cell affects the
effective resistance of the memory cell, the method comprising:
receiving a binary value to be stored in the memory cell;
determining a target discharge time corresponding to the binary value; and
storing a characteristic parameter in the memory cell such that an electron discharge time through an electronic circuit formed,
at least partially, by the memory cell, is substantially equal to the target discharge time.
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