| US 7,602,631 B2 | ||
| Multi-level memory cell utilizing measurement time delay as the characteristic parameter for level definition | ||
| Matthew J. Breitwisch, Yorktown Heights, N.Y. (US); Chung H. Lam, Peekskill, N.Y. (US); and Bipin Rajendran, White Plains, N.Y. (US) | ||
| Assigned to International Business Machines Corporation, Armonk, N.Y. (US) | ||
| Filed on Sep. 18, 2007, as Appl. No. 11/857,356. | ||
| Prior Publication US 2009/0073784 A1, Mar. 19, 2009 | ||
| Int. Cl. G11C 11/00 (2006.01) | ||
| U.S. Cl. 365—148 [365/203; 365/204] | 16 Claims |
| 1. A memory array comprising:
a plurality of memory cells, each memory cell is configured to store a characteristic parameter;
a writing unit configured to receive a binary value for a selected memory cell and determine a target discharge time corresponding
to the binary value;
a controller unit configured to form an electronic circuit for the selected memory cell in the memory array such that an electron
discharge time of the electronic circuit is dependent on the stored characteristic parameter of the selected memory cell;
a detecting unit configured to measure the electron discharge time of the electronic circuit for the selected memory cell;
an output unit configured to output the binary value represented by the stored characteristic parameter for the selected memory
cell based on the measured electron discharge time of the electronic circuit; and
wherein the writing unit is further configured to write the characteristic parameter in the selected memory cell such that
the electron discharge time through the electronic circuit is substantially equal to the target discharge time.
|