| US 7,602,252 B2 | ||
| Sigma delta modulator, fractional frequency synthesizer and sigma delta modulating method | ||
| Hidenori Sakai, Tokyo (Japan) | ||
| Assigned to Advantest Corporation, Tokyo (Japan) | ||
| Filed on Sep. 07, 2007, as Appl. No. 11/851,396. | ||
| Claims priority of application No. 2006-276826 (JP), filed on Oct. 10, 2006. | ||
| Prior Publication US 2008/0084247 A1, Apr. 10, 2008 | ||
| Int. Cl. H03L 7/195 (2006.01); H03M 3/02 (2006.01) | ||
| U.S. Cl. 331—1A [341/143; 327/156] | 7 Claims |
| 1. A sigma delta modulator that outputs an output signal obtained by performing sigma delta modulation on an input signal,
comprising:
a plurality of accumulators that are serially connected to one another; and
an output signal generating section that generates the output signal based on comparison result signals respectively output
from the accumulators,
wherein
each of the accumulators integrates values of signals being input and when an integration value is not less than a reference
value, outputs the comparison result signal with a predetermined value and subtracts the value of the comparison result signal
from the integration value,
the value of the input signal is at least input into the accumulator connected to a predetermined stage,
the integration value of one of the accumulators is input into the following accumulator, and
at least one of the accumulators includes a low-pass IIR filter that removes a predetermined frequency component higher than
a predetermined frequency in a waveform of the integration value,
each of the accumulators comprises:
an accumulation register;
an addition section that adds a value according to a value stored on the accumulation register to the value of the input signal
and outputs the integration value;
a comparing section that compares the integration value and the reference value and outputs, when the integration value is
not less than the reference value, the comparison result signal with the predetermined value; and
a subtraction section that subtracts the value of the comparison result signal output from the comparing section from the
integration value input into the comparing section and stores its result on the accumulation register, and
the low-pass filter comprises:
a first multiplication section that multiplies a first coefficient by the value stored on the accumulation register and inputs
its result into the addition section;
a second multiplication section that multiplies a second coefficient by the value stored on the accumulation register and
outputs its result; and
an in-filter addition section that adds the value output from the second multiplication section to the value output from the
subtraction section and stores its result on the accumulation register.
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