| US 7,602,172 B2 | ||
| Test apparatus having multiple head boards at one handler and its test method | ||
| Ae-Yong Chung, Chungcheongnam (Korea, Republic of); Sung-Ok Kim, Chungcheongnam (Korea, Republic of); Kyeong-Seon Shin, Kyunggi-do (Korea, Republic of); and Jeong-Ho Bang, Kyunggi-do (Korea, Republic of) | ||
| Assigned to Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do (Korea, Republic of) | ||
| Filed on Apr. 24, 2008, as Appl. No. 12/109,299. | ||
| Application 12/109299 is a division of application No. 11/092067, filed on Mar. 28, 2005, granted, now 7,378,864. | ||
| Application 11/092067 is a division of application No. 10/672994, filed on Sep. 25, 2003, granted, now 6,903,567, filed on Jun. 07, 2005. | ||
| Claims priority of application No. 10-2002-0058349 (KR), filed on Sep. 26, 2002. | ||
| Prior Publication US 2008/0197874 A1, Aug. 21, 2008 | ||
| Int. Cl. G01R 31/26 (2006.01) | ||
| U.S. Cl. 324—158.1 [324/765; 324/73.1] | 4 Claims |
| 1. A test apparatus for testing a plurality of semiconductor devices loaded on one handler connected to a tester, the handler
comprising:
at least first and second head boards on which semiconductor devices can be loaded for testing; and
a test head to generate selection signals corresponding to different head boards for sequential test cycles;
wherein semiconductor devices loaded on the first head board are tested in response to one selection signal, and semiconductor
devices loaded on the second head board are tested in response to another selection signal;
wherein the handler has the capability to sort, according to a test result obtained for the first head board, semiconductor
devices loaded on the first head board while semiconductor devices loaded on the second head board are selectively tested
in response to the selection signal corresponding to the second head board.
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