| US 7,602,042 B2 | ||
| Nonvolatile memory device, array of nonvolatile memory devices, and methods of making the same | ||
| Seung-Eon Ahn, Seoul (Korea, Republic of); In-Kyeong Yoo, Suwon-si (Korea, Republic of); Young-Soo Joung, Seoul (Korea, Republic of); Young-Kwan Cha, Yongin-si (Korea, Republic of); Myoung-Jae Lee, Suwon-si (Korea, Republic of); David Seo, Yongin-si (Korea, Republic of); and Sun-Ae Seo, Hwaseong-si (Korea, Republic of) | ||
| Assigned to Samsung Electronics Co., Ltd., Gyeonggi-do (Korea, Republic of) | ||
| Filed on Nov. 10, 2005, as Appl. No. 11/270,459. | ||
| Claims priority of application No. 10-2004-0091497 (KR), filed on Nov. 10, 2004. | ||
| Prior Publication US 2006/0098472 A1, May 11, 2006 | ||
| Int. Cl. H01L 23/62 (2006.01) | ||
| U.S. Cl. 257—530 [257/529; 257/350; 257/358] | 21 Claims |
| 8. A nonvolatile memory device comprising:
a lower electrode;
an array of a nonvolatile memory device, the array comprising:
at least two bit lines arranged at regular intervals on a substrate;
at least two word lines arranged at regular intervals and disposed across the bit lines;
a resistor structure including a data storage layer disposed on the bit lines at each of the intersections of the bit lines
and word lines, the data storage layer including at least one of NiO, TiO2, HfO, ZrO, ZnO, WO3, CoO, and Nb2O5; and
a diode structure disposed in contact with the resistor structure and the word lines, the diode structure including
a first oxide layer disposed on the resistor structure, and
a second oxide layer disposed on the first oxide layer.
|