| US 7,602,026 B2 | ||
| Memory cell, semiconductor memory device, and method of manufacturing the same | ||
| Shinji Horii, Fukuyama (Japan); Takashi Yokoyama, Fukuyama (Japan); and Tetsuya Ohnishi, Fukuyama (Japan) | ||
| Assigned to Sharp Kabushiki Kaisha, Osaka (Japan) | ||
| Filed on Jun. 26, 2006, as Appl. No. 11/474,414. | ||
| Claims priority of application No. 2005-184866 (JP), filed on Jun. 24, 2005. | ||
| Prior Publication US 2006/0289942 A1, Dec. 28, 2006 | ||
| Int. Cl. H01L 23/62 (2006.01) | ||
| U.S. Cl. 257—379 [257/324; 257/529; 257/E23.149; 365/158] | 13 Claims |
| 1. A memory cell in a semiconductor memory device comprising:
a variable resistor element configured so that a variable resistor body is sandwiched between a first electrode and a second
electrode, and a transistor element capable of controlling a flow of current in the variable resistor element, wherein
the transistor element and the variable resistor element are placed one over the other along a direction in which the first
electrode, the variable resistor body, and the second electrode of the variable resistor element are layered,
one of the first electrode and the second electrode of the variable resistor element is connected to one electrode of the
transistor element;
wherein the variable resistor element is configured so that the variable resistor body is arranged on the second electrode
and the first electrode is arranged on the variable resistor body, and
the first electrode contains at least one type of material from precious metals in the platinum group metals, single metals
selected from Ag, Al, Cu, Ni, Ti, and Ta or alloys of these, oxide conductors selected from Ir, Ru, Re, and Os, and oxide
conductors selected from SRO(SrRuO3), LSCO((LaSr)CoO3), and YBCO(YbBa2Cu3O7).
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