a semiconductor substrate of a first conductivity type having an upper surface;

a first doped region of the first conductivity type that extends downwardly from the upper surface;

a gate overlying the first doped region and having a gate dielectric on the upper surface, an overlying dielectric layer on the gate dielectric, and a gate conductor, wherein a lateral extent of the gate extends beyond the first doped region and over portions of second doped regions that are laterally adjacent to the first doped region at the upper surface;

the second doped regions of a second opposite conductivity type extending downwardly from the upper surface and initially formed in the substrate beyond the lateral extent of the gate, wherein the first doped region and the second doped regions meet under the gate after exposure to a high temperature drive process, and wherein a charge equality condition is present in the first doped region and the second doped regions because a net active impurity concentration N_first in the first doped region of lateral length L_first and a net active impurity concentration N_second in the second doped regions of lateral length L_second satisfy a first relationship (N_second*L_second)=k₁*(N_first*L_first), where k₁ has a value in a range of about 0.6<k₁<1.4, and also satisfy a second relationship that a depth of the first doped region is about equal to a depth of the second doped regions; and

a drain region of the first conductivity type located in the semiconductor substrate beneath the first doped region and the second doped regions, wherein the drain region is separated from the first doped region and the second doped regions by a portion of the semiconductor substrate that overlies the drain region and is beneath the first doped region and the second doped regions, and wherein the charge equality condition is not present in the portion of the semiconductor substrate that overlies the drain region and is beneath the first doped region and the second doped regions.