| US 7,602,005 B2 | ||
| Memory devices including spacer-shaped electrodes on pedestals and methods of manufacturing the same | ||
| Byung-Kyu Cho, Seoul (Korea, Republic of); Tae-Yong Kim, Suwon-si (Korea, Republic of); and Choong-Ho Lee, Seongnam-si (Korea, Republic of) | ||
| Assigned to Samsung Electronics Co., Ltd., (Korea, Republic of) | ||
| Filed on Jun. 06, 2007, as Appl. No. 11/759,044. | ||
| Claims priority of application No. 10-2006-0058395 (KR), filed on Jun. 28, 2006. | ||
| Prior Publication US 2008/0001211 A1, Jan. 03, 2008 | ||
| Int. Cl. H01L 27/115 (2006.01) | ||
| U.S. Cl. 257—315 [257/E27.103] | 22 Claims |
| 1. A memory device comprising:
a substrate including closely spaced apart trenches that extend in a first direction to define closely spaced apart pedestals
therebetween that extend in the first direction, a respective pedestal including opposing sidewalls and a pedestal top therebetween,
the trench having first and second sidewalls opposite to each other;
a plurality of closely spaced apart bit lines in the substrate having a linear shape that extend in a second direction substantially
perpendicular to the first direction across the spaced apart trenches and across the pedestals therebetween and that extend
in a respective pedestal along the opposing sidewalls and along the pedestal top;
a plurality of closely spaced apart electrodes on the plurality of opposing sidewalls that extend in the first direction and
that are thicker remote from the pedestal tops than adjacent the pedestal tops, wherein a first electrode of the electrodes
is on the first sidewall of the trench, a second electrode of the electrodes is on the second sidewall of the trench, and
the first and second electrodes are spaced apart from each other; and
a plurality of memory cells located at intersections of the bit lines and the electrodes.
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