| US 7,601,627 B2 | ||
| Method for reduction of soft error rates in integrated circuits | ||
| Cyril Cabral, Jr., Mahopac, N.Y. (US); Michael S. Gordon, Yorktown Heights, N.Y. (US); and Kenneth P. Rodbell, Sandy Hook, Conn. (US) | ||
| Assigned to International Business Machines Corporation, Armonk, N.Y. (US) | ||
| Filed on Mar. 19, 2008, as Appl. No. 12/51,040. | ||
| Application 12/051040 is a division of application No. 11/183647, filed on Jul. 18, 2005, granted, now 7,381,635. | ||
| Prior Publication US 2008/0164584 A1, Jul. 10, 2008 | ||
| Int. Cl. H01L 21/44 (2006.01) | ||
| U.S. Cl. 438—613 [438/555; 438/614; 257/E23.021; 257/E23.169] | 9 Claims |
| 1. A method, comprising:
providing a test device, said test device comprising:
a semiconductor substrate; and
a stack of one or more wiring levels stacked from a lowermost wiring level to an uppermost wiring level, said lowermost wiring
level on a top surface of said substrate;
selecting an energy of alpha particles of a given energy to be stopped from penetrating through said stack of one or more
wiring levels;
bombarding said semiconductor substrate with a flux of said alpha particles of said selected energy; and
determining a combination of a thickness of a blocking layer and a volume percent of metal wires in said blocking layer sufficient
to stop a predetermined percentage of alpha particles of said maximum energy striking a top surface of said blocking layer
from penetrating through said stack of one or more wiring levels.
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