| US 7,601,606 B2 | ||
| Method for reducing the trap density in a semiconductor wafer | ||
| Francois Brunier, Grenoble (France); Vivien Renauld, Pontcharra (France); and Jean Marc Waechter, Saint Vincent De Mercuze (France) | ||
| Assigned to S.O.I.Tec Silicon on Insulator Technologies, Bernin (France) | ||
| Filed on Sep. 28, 2006, as Appl. No. 11/541,199. | ||
| Application 11/541199 is a continuation of application No. PCT/IB2005/000434, filed on Feb. 03, 2005. | ||
| Prior Publication US 2007/0020886 A1, Jan. 25, 2007 | ||
| Int. Cl. H01L 21/76 (2006.01) | ||
| U.S. Cl. 438—407 [438/423] | 19 Claims |
| 1. A method for manufacturing a mutilayer semiconductor wafer having reduced interfacial trap densities, the method comprising:
providing a multilayer wafer comprising a surface that includes a capping oxide layer, an active semiconductor layer underlying
the capping layer, a first internal interface, and at least one second internal interface, each interface being between a
semiconductor layer and an adjoining insulator layer, with the first interface located between the capping oxide layer and
the underlying active semiconductor layer, the second interface of the multilayer wafer located between an active semiconductor
layer and an underlying buried oxide layer, and the second interface being further removed from the surface of the multilayer
wafer than is the first internal interface;
introducing a controlled proportion of a species into a generally neutral atmosphere, wherein the species is an element that
is different than the atmosphere; and
exposing the wafer to the atmosphere and species at a selected temperature between about 800° C. and about 1200° C., wherein
the introduced species migrates at least to the second interface, reducing the interfacial trap density at that interface.
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