| US 7,601,598 B2 | ||
| Reverse metal process for creating a metal silicide transistor gate structure | ||
| Werner Juengling, Boise, Id. (US); and Richard H. Lane, Boise, Id. (US) | ||
| Assigned to Micron Technology, Inc., Boise, Id. (US) | ||
| Filed on Oct. 01, 2007, as Appl. No. 11/905,475. | ||
| Application 11/905475 is a division of application No. 11/033525, filed on Jan. 12, 2005, granted, now 7,288,817. | ||
| Application 11/033525 is a division of application No. 10/673362, filed on Sep. 30, 2003, granted, now 7,067,880. | ||
| Application 10/673362 is a division of application No. 10/230203, filed on Aug. 29, 2002, granted, now 6,821,855. | ||
| Prior Publication US 2008/0038893 A1, Feb. 14, 2008 | ||
| Int. Cl. H01L 21/336 (2006.01) | ||
| U.S. Cl. 438—289 [438/303; 438/305; 257/E21.165; 257/E21.437] | 23 Claims |
| 1. A method of fabricating a gate structure of a transistor, said method comprising:
forming an oxide layer over a substrate;
forming a conducting layer over said oxide layer;
forming an insulating layer over said conducting layer;
removing portions of said oxide layer, said conducting layer, and said insulating layer to form a gate stack, said gate stack
having an oxide layer, a conducting layer, and an insulating layer;
removing said insulating layer from said gate stack to expose said conducting layer;
providing a metal-containing layer on said exposed conducting layer which can form a silicide; and
forming at least one channel implant region underneath said gate stack.
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