| US 7,601,592 B2 | ||
| Method for forming multi-gate non-volatile memory devices using a damascene process | ||
| Chang-Woo Oh, Suwon (Korea, Republic of); Dong-Gun Park, Seongnam (Korea, Republic of); Dong-Won Kim, Seongnam (Korea, Republic of); and Yong-Kyu Lee, Seoul (Korea, Republic of) | ||
| Assigned to Samsung Electronics Co., Ltd., (Korea, Republic of) | ||
| Filed on Jun. 09, 2008, as Appl. No. 12/135,295. | ||
| Application 12/135295 is a division of application No. 11/602032, filed on Nov. 20, 2006, granted, now 7,402,493. | ||
| Application 11/602032 is a division of application No. 11/007760, filed on Dec. 08, 2004, granted, now 7,161,206, filed on Jan. 09, 2007. | ||
| Claims priority of application No. 10-2004-0025095 (KR), filed on Apr. 12, 2004. | ||
| Prior Publication US 2008/0242075 A1, Oct. 02, 2008 | ||
| Int. Cl. H01L 21/336 (2006.01); H01L 21/3205 (2006.01); H01L 21/4763 (2006.01); H01L 29/80 (2006.01) | ||
| U.S. Cl. 438—259 [438/587; 438/593; 438/594; 438/596; 257/239; 257/261; 257/E29.129] | 10 Claims |
| 1. A method for forming the semiconductor memory device comprising:
etching a predetermined depth of an exposed semiconductor substrate using a capping pattern formed on the semiconductor substrate
and forming a device isolating layer to construct a semiconductor fin surrounded by the device isolating layer and the capping
pattern;
forming a material pattern including a trench exposing the capping pattern and a portion of the device isolating layer, on
the capping pattern and the device isolating layer;
etching the device isolating layer exposed by the trench to expose sides of the semiconductor fin;
sequentially forming a conformal tunneling insulating layer, a charge storage layer and a blocking insulating layer on the
exposed sides of the semiconductor fin and the capping pattern; and
forming a gate electrode layer on the blocking insulating layer to fill the trench.
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