| US 7,601,583 B2 | ||
| Transistor structure of memory device and method for fabricating the same | ||
| Se Aug Jang, Icheon-si (Korea, Republic of); Yong Soo Kim, Suwon-si (Korea, Republic of); Jae Geun Oh, Icheon-si (Korea, Republic of); Jae Sung Rohh, Gwacheon-si (Korea, Republic of); and Hyun Chul Sohn, Seoul (Korea, Republic of) | ||
| Assigned to Hynix Semiconductor Inc., Icheon-si (Korea, Republic of) | ||
| Filed on Dec. 21, 2007, as Appl. No. 11/962,100. | ||
| Application 11/962100 is a division of application No. 11/201951, filed on Aug. 10, 2005, granted, now 7,332,755. | ||
| Claims priority of application No. 10-2005-0036056 (KR), filed on Apr. 29, 2005. | ||
| Prior Publication US 2008/0096355 A1, Apr. 24, 2008 | ||
| Int. Cl. H01L 29/72 (2006.01) | ||
| U.S. Cl. 438—231 [438/163; 438/197; 438/221; 438/225; 438/300; 438/283; 438/585; 438/700; 438/735 H] | 12 Claims |
| 1. A method for fabricating a semiconductor memory device, the method comprising:
forming an active area protruding from a predetermined portion of a semiconductor substrate by etching the semiconductor substrate;
forming a field oxide layer defining the active area in the semiconductor substrate;
forming a recess in a channel area provided in the active area;
etching the field oxide layer in such a manner that the field oxide layer is positioned lower than an upper surface of the
active area including the recess;
forming a gate insulation layer over the active area in which the recess and the upper surface of the active area are exposed;
and
forming a gate electrode over the gate insulation layer and the field oxide layer in such a manner that the gate electrode
extends across an upper portion of the active area and overlaps with the recess.
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