| US 7,601,569 B2 | ||
| Partially depleted SOI field effect transistor having a metallized source side halo region | ||
| Jin Cai, Cortlandt Manor, N.Y. (US); Wilfried Haensch, Somers, N.Y. (US); and Amlan Majumdar, White Plains, N.Y. (US) | ||
| Assigned to International Business Machines Corporation, Armonk, N.Y. (US) | ||
| Filed on Jun. 12, 2007, as Appl. No. 11/761,568. | ||
| Prior Publication US 2008/0308867 A1, Dec. 18, 2008 | ||
| Int. Cl. H01L 21/335 (2006.01); H01L 21/00 (2006.01); H01L 21/338 (2006.01); H01L 21/8234 (2006.01) | ||
| U.S. Cl. 438—149 [438/151; 438/180; 438/237] | 6 Claims |
| 1. A method of forming a semiconductor structure comprising:
providing a semiconductor-on-insulator substrate having a top semiconductor layer having a doping of a first conductivity
type;
forming a gate conductor on said top semiconductor layer;
forming a source side halo region and drain side halo region, each having a doping of said first conductivity type, in said
top semiconductor layer;
forming at least one gate spacer on said gate conductor; and
forming a deep source region and a deep drain region, each having a doping of a second conductivity type, in said top semiconductor
layer by angled ion implantation, wherein said second conductivity type is the opposite of said first conductivity type, said
deep source region is formed offset away from an edge of said at least one gate spacer and does not contact said at least
one gate spacer, and wherein said deep drain region is formed directly below said at least one gate spacer and directly contacts
said at least one gate spacer.
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