a semiconductor substrate;

a memory region provided on said semiconductor substrate; and

a logic region provided on said semiconductor substrate;

wherein said memory region includes:

a first transistor provided on said semiconductor substrate, a first insulating layer covering said first transistor,

a plurality of first conductive plugs connected to a diffusion layer of said first transistor and terminated on an upper surface of said first insulating layer,

a capacitor element provided on said first insulating layer, and

a bit line provided on said first insulating layer; said logic region includes:

a second transistor provided on said semiconductor substrate and covered with said first insulating layer,

a plurality of second conductive plugs connected to a diffusion layer of said second transistor and terminated on an upper surface of said first insulating layer, and

an upper interconnect provided on said second conductive plugs via a multilayer insulating layer;

wherein said plurality of first conductive plugs includes a plug connected to said capacitor element and a plug connected to said bit line and an isolated plug connected neither to said capacitor element nor to said bit line;

wherein said logic region includes a plurality of connected plugs and a plurality of isolated plugs;

wherein said plurality of connected plugs includes at least one of said second conductive plugs and at least one conductive plug that connects said one second conductive plug with said upper interconnect; and

wherein said plurality of isolated plugs includes at least another of said second conductive plugs, said plurality of isolated plugs are not connected to said upper interconnect and are terminated at a different level of said multilayer insulating layer than said plurality of connected plugs.