| US 7,432,202 B2 | ||
| Method of substrate manufacture that decreases the package resistance | ||
| Bijay S. Saha, Chandler, Ariz. (US); Munehiro Toyama, Ibarakiken (Japan); Ehab A. Nasir, Mesa, Ariz. (US); Omar J. Bchir, Chandler, Ariz. (US); and Charavana K. Gurumurthy, Gilbert, Ariz. (US) | ||
| Assigned to Intel Corporation, Santa Clara, Calif. (US) | ||
| Filed on Dec. 28, 2005, as Appl. No. 11/320,273. | ||
| Prior Publication US 2007/0148971 A1, Jun. 28, 2007 | ||
| Int. Cl. H01L 21/44 (2006.01) | ||
| U.S. Cl. 438—686 [257/768] | 13 Claims |
| 1. A method comprising:
forming a coating on a land contact of a package substrate configured to connect to a circuit die, the land contact comprising
copper, the coating comprising a first material disposed between a first layer and a second layer, and each of the first layer
and the second layer being made of a second material comprising gold.
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