| US 7,600,174 B2 | ||
| Apparatus and method for encoding and decoding a block low density parity check code | ||
| Gyu-Bum Kyung, Suwon-si (Korea, Republic of); Hong-Sil Jeong, Suwon-si (Korea, Republic of); Dong-Seek Park, Yongin-si (Korea, Republic of); and Jae-Yoel Kim, Gunpo-si (Korea, Republic of) | ||
| Assigned to Samsung Electronics Co., Ltd, (Korea, Republic of) | ||
| Filed on Aug. 10, 2005, as Appl. No. 11/201,663. | ||
| Claims priority of application No. 10-2004-0062977 (KR), filed on Aug. 10, 2004. | ||
| Prior Publication US 2006/0036927 A1, Feb. 16, 2006 | ||
| Int. Cl. H03M 13/00 (2006.01) | ||
| U.S. Cl. 714—758 [714/781] | 5 Claims |
| 1. A method for generating a block low density parity check (LDPC) code, comprising the steps of:
receiving an information word vector; and
generating a first parity vector such that a vector generated by multiplying a matrix generated by summing all rows of a fourth
matrix for generating a first matrix included in a generation matrix, per block by a transpose vector of the information word
vector as a vector generated by cyclic-shifting a transpose vector of the first parity vector by a predetermined value, the
first matrix is generated by multiplying the fourth matrix, mapped to the information word vector of a parity check matrix
corresponding to a length to be applied when generating the information word vector into a block LDPC code, by a predetermined
fifth matrix;
generating a second parity vector using back substitution by a third matrix mapped to the second parity vector in the generation
matrix, the third matrix has a dual-diagonal structure, the third matrix is generated by multiplying a seventh matrix mapped
to the second parity vector of the parity check matrix by the fifth matrix; and
generating the block LDPC code by connecting the first parity vector and the second parity vector to the information word
vector;
wherein the generation matrix is generated by modifying the parity check matrix corresponding to the length to be applied
when generating the information word vector into the block LDPC code,
wherein the generation matrix represents a multiplication of a new matrix F and the parity check matrix, exponents of all
non-zero permutation matrices corresponding to a last block of the generation matrix increased by am through a modulo-Ns operation, Ns is the number of rows or columns of a permutation matrix corresponding to each of partial blocks constituting the generation
matrix, identity matrices are located along a diagonal line of the generation matrix except for a last part, and am are exponents of a permutation matrix located in the last part of a diagonal line in the generation matrix, and
wherein the generation matrix includes a second matrix mapped to the first parity vector,
the second matrix is generated by multiplying a sixth matrix mapped to the first parity vector of the parity check matrix
by the fifth matrix.
|